1. Technical Field
This invention relates generally to packet switching devices, and more particularly to a packet switch which can be scaled up to handle a large number of ports without a corresponding decrease in performance. The invention provides a technique for detecting high traffic levels between two ports and diverting packets between such ports through a dedicated channel.
2. Related Information
Packet switching techniques are conventionally used to transmit various types of digital data such as digitized voice, computer data, and video signals. Data (e.g., a telephone voice signal) is broken up into packets each of a specified size, wherein each packet typically includes, in addition to the digital data, a header indicating a destination address to which the packet should be sent. A packet switching network made up of packet switches can be used to route packets to their respective destinations without delay. See, for example, U.S. Pat. No. 5,544,160 to Cloonan et al., entitled "Terabit per Second Packet Switch".
Packet switches may also be used in smaller communication networks to route data between devices. As one example, an interoffice videoconferencing system may have a requirement to selectively transmit digitized video and audio information to one or more recipients through a centralized switch. A packet switch can be designed to handle such digitized information, so that packets comprising a video signal from one video conference participant are switched to all participants of the video conference.
As the size of packet switching networks has grown, the complexity and processing requirements of packet switching devices has increased. For example, the number of ports required for a particular packet switch has increased, requiring faster processors to handle the increased traffic.
Conventional packet switches (i.e., devices which route packets of digital data between two sets of ports) are well known. FIG. 1 shows in simplified form a conventional packet switch architecture including a CPU 101, a routing table 102, buffer memory 103, data bus 104, and packet interfaces 105 through 111 each corresponding to a port. Packets arrive at a port (e.g., port 1) and are routed to a destination port (e.g., port 2) based on information contained in packet headers.
Most packet switches rely on fast software to route packets. As shown in FIG. 1, for example, incoming packets are received by packet interfaces 105 through 111 and interpreted by CPU 101. CPU 101 temporarily stores incoming packets into buffer memory 103 and examines each packet header to determine which port the packet should be routed to for output. This examination usually involves searching a look-up table of addresses versus ports stored in routing table 102. The table includes a list of addresses and ports which are most advantageous to route the packet for a given address. Following the look-up operation, the packet is placed in the correct packet interface and sent to the destination port. Special messages can be transmitted to the packet switch to change routing table 102, thus changing the network routing parameters.
One problem with the conventional architecture of FIG. 1 is that it can take a long time to sort through routing table 102. As a network grows, the number of potential distant packet addresses grows. In fact, it may be that the packet routing table can be billions of addresses long, severely bogging down CPU 101.
The time it takes to receive and store packets while the routing process is underway will limit the number of ports that a packet switch can support. It also limits the number of packets that can be routed per second. A given CPU has a finite processor bandwidth Z. This bandwidth will allow the CPU to successfully route X packets per second. Each packet interface has a bandwidth or maximum packet speed Y in packets per second. Thus, the number of ports N that can be successfully serviced by this type of packet switch is limited to N(max)=X/Y.
A packet switch based on the architecture of FIG. 1 can only be scaled as far as the CPU bandwidth is scaled. This is difficult, as there is a limit on the processing bandwidth of a single CPU. Consequently, packet switches based on the general architecture shown in FIG. 1 cannot be easily scaled to support a large number of ports or addresses.